Intel's Nehalem Processor Architecture

The Core i5 and i7 Nehalem processor series is the first multi-core design from Intel to have its cores joined in a single die rather than to join multiple cores together, potentially speeding up operations with multiple program threads by cutting back on the time spent moving data between cores.

See, Intel's original Core 2 quads are actually a pair of completely separate dual-core CPU dies glued together in a single processor package. From an engineering perspective, not very sexy.

This is the reason that inter-core communications on the older Core 2 processor series is a little intricate. Between two cores on the same die, bandwidth is massive and latency low. But if cores on separate dies need a chat, the communication path is routed off the CPU through the north bridge chip on the motherboard. Not ideal, so the new approach is definitely more elegant and efficient.

The Intel Core i7 and Core i5 (Bloomfield and now Lynnfield) processors debut with the following features:

• Four processing cores
• Support for SMT (simultaneous multi-threading), allowing up to 8 threads to be processed simultaneously
• 32 KB instruction + 32 KB data L1 cache per core
• 256 KB L2 cache per core
• Large 8 MB L3 cache shared by all 4 cores
• An integrated memory controller (IMC) supporting two or three channels of DDR3 memory
  - Memory clock speeds of up to 1333 MHz
  - Memory bandwidth of up to 32 GB/s
  - Up to 6 memory sockets for Socket 1366 Core i7 series 900
  - Up to 4 memory sockets for Socket 1156 Core i5/i7 series 700/800
• The new Intel Quick Path Interconnect
• Addition of 7 new SSE4 instructions
• Monolithic processor design (all four cores on a single die)
• Fabricated using Intel's 45nm high-k process technology

What you need to remember is that the architecture family codename is called Nehalem, and it will allow for many more products to be released in the next year or two. We will see higher clock frequencies, yet also 2, 6 and likely 8 (physical) core versions.

Architectural changes. The 731 million transistors encounting Core i7 900 series processors are built up-on a 45nm fabrication processes, but by itself that is nothing new as the latest Core 2 Quad processors are on the same fabrication.

Lynnfield based Core i5/7 series 700 and 800 have 774 million transistors all jammed into a die size of 296mm² (45nm fab). And yes, Intel is already working on a move to 32nm, Clarksdale. All Nehalem chips will pack 64KB of L1 cache and 256KB of L2 cache. Those are supplemented by a large pool of shared L3 cache, which in the case of the quad-core model is 8MB.

A good number of things have changed in its architecture. The biggest being Quick Path, the move forwards to an integrated dual or triple-channel DDR3 memory controller allowing the product heaps of memory bandwidth and Hyper Threading (Pentium 4 era technology).

Nehalem brings in some improvements which signal important changes in the Intel approach to CPU and system scaling and DRAM memory management. Let's walk through them.

Core i7 series 900 processor die

Core i5 and i7 series 700/800 processor die